Architecture - Compute numbers

• 1.5 TeraOPS (1.5x1012) 8 bit multiplies and adds

  • LEE + PE
  • 12K bit data-path (8x1536)

• 600 Gigabytes/sec on chip DRAM bandwidth

  • 50k bit wide data-bus (32x1536)

• 1.2 Terabytes/sec PE register file data bandwidth

• 1.2 Terabytes/sec inter PE data bandwidth

• ɯ GigaFlops (IEEE compatible)

  • Can be faster with custom format

• 7 GMACs (16x16)

• 150M 3D Transformations/sec

• 50M Tris/sec

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