Massively Parallel Computing on the FUZION Chip

8/25/99


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Table of Contents

Massively Parallel Computing on the FUZION Chip

Overview

Thoroughbred Technology

PPT Slide

Architecture - System EPU

Architecture - Core

Architecture - Blocks

Architecture - LEE

Architecture - PE

Characteristics Key points

Characteristics - Silicon

PPT Slide

Architecture - Compute numbers

Graphics Applications

SIMD OpenGL

SIMD OpenGL

SIMD OpenGL

Silicon Schedule

Future Graphics

Future - Silicon

Future - Software Development Kit

Future - Applications

Future price/performance

Conclusion

Author: Ray McConnell

Other information:
Presentation for SIGGRAPH Eurographics 1999 Hardware Workshop in Computer Graphics